This invention relates to programmable logic devices. More particularly, this invention relates to localized conductors associated with logic array blocks on programmable logic devices.
Programmable logic array devices are integrated circuits that are programmable by a user to perform various logic functions. At their most basic level, programmable logic array devices contain programmable components, such as erasable programmable read-only (EPROM) transistors, electrically erasable programmable read-only (EEPROM) transistors, random access memory (RAM) transistors or cells, fuses, and antifuses. In order to provide higher level functions, the programmable components are organized into various groups of components that are electrically connected to one another by programmable interconnections.
Programmable logic array integrated circuit devices are described in commonly-assigned copending U.S. patent application Ser. No. 08/672,676, filed Jun. 28, 1996 and U.S. Pat. No. 5,689,195. U.S. patent application Ser. No. 08/672,676 and U.S. Pat. No. 5,689,195 show how small regions of logic called logic elements can be formed based on look-up table and register logic. Somewhat larger regions of logic called logic array blocks (LABs) are formed from the logic elements. Each logic array block contains eight logic elements. Logic array blocks are arranged in rows and columns on the programmable logic array device. Associated rows and columns of interblock conductors are used to interconnect the logic array blocks.
Each logic array block generally has two types of associated localized conductors used by the logic within that block. The first type of localized conductors are known as logic array block conductors. Logic array block conductors route signals from rows of horizontal interblock conductors onto logic element input conductors. The second type of localized conductors are known as local conductors. Local conductors primarily route output signals from the logic elements to the inputs of other logic elements within the same logic array block. The logic array block and local conductors run perpendicular to the input conductors of the logic elements in the block. Each logic array block conductor and local conductor has a programmable connection to each of the logic element input conductors in the logic array block.
There must be a sufficient number of logic array block and local conductors associated with each logic array block to implement logic designs of various sizes. In practice, a typical logic array block uses about 10 associated logic array block conductors to convey signals. However, in order to accommodate the largest logic designs that are encountered, it is necessary to provide about 20 logic array block conductors for each logic array block. Similarly, a typical logic array block has eight associated local conductors, even though fewer than eight local conductors are used to implement many logic designs. Providing numerous logic array block conductors and local conductors makes the localized conductor arrangement flexible enough to accommodate most desired logic designs. However, providing too many conductors per logic array block wastes interconnection resources, because a significant number of the conductors and programmable connections between conductors will remain unused in each block.
It is therefore an object of the present invention to provide an improved localized conductor arrangement for the logic array blocks on a programmable logic device.